Decreasing device size and increasing device density has traditionally been a high priority for the manufacturing of integrated circuits. Optical lithography has been the driving force for device scaling. Conventional optical lithography is limited to about 80 nm pitch for single exposure patterning. Whilst double and other multi-patterning processes can realize smaller pitch, these approaches are expensive and more complex.
Directed self-assembly (DSA), a technique which aligns self-assembling polymeric materials on a lithographically defined guide pattern, is a potential option for extending current optical lithography beyond its pitch and resolution limits. The self-assembling materials, for example, are block copolymers (BCPs) that consist of “A” homopolymer covalently attached to “B” homopolymer, which are coated over a lithographically defined guide pattern on a semiconductor substrate. The lithographically defined guide pattern is a pre-pattern that is encoded with spatial chemical and/or topographical information and serves to direct the self-assembly process and the pattern formed by the self-assembling materials. Subsequently, by annealing the DSA polymers, the A polymer chains and the B polymer chains undergo phase separation to form an A polymer region and a B polymer region that are registered to the guide pattern. Then, by removing either the A polymer region or the B polymer region by wet chemical or plasma-etch techniques, a mask is formed for transferring the nanopattern to the underlying substrate.
One DSA technique is graphoepitaxy in which self-assembly is directed by topographical features that are formed overlying a semiconductor substrate. This technique is used, for example, to create contact holes or vias that can be subsequently filled with conductive material for forming electrical connections between one or more layers of the semiconductor substrate. In particular, the topographical features are formed overlying the semiconductor substrate to define confinement wells. The confinement wells are filled with a BCP that is subsequently phase separated to form, for example, etchable cylinders or other etchable features that are each formed of either the A polymer region or the B polymer region of the BCP. The etchable cylinders are removed to form openings and define a mask for etch transferring the openings to the underlying substrate. To ensure process uniformity, it is desirable to deposit a uniform thickness of the BCP without, for example, overfilling the confinement wells between the topographical features. The local density of the confinement wells generally varies across the semiconductor substrate with some areas having a higher density of confinement wells (e.g., relatively more confinement wells per unit area) and other areas having a lower density of confinement wells (e.g., relatively fewer confinement wells per unit area). In the lower density areas, the confinement wells are particularly susceptible to overfilling with the BCP. One solution is to add additional confinement wells to these areas to increase the local density of confinement wells. However, this may be undesirable because the artificially added confinement wells will generally result in additional features in the mask that will be etch transferred to the underlying substrate resulting, for example, in unintended electrical connections between layers of the substrate.
Accordingly, it is desirable to provide methods for fabricating integrated circuits including formation of topographical features for directed self-assembly with improved process uniformity for filling confinement wells formed by the topographical features with block copolymer. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.